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Cypress Semiconductor /psoc63 /BLE /BLESS /MT_STATUS

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Interpret as MT_STATUS

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BLESS_STATE)BLESS_STATE 0MT_CURR_STATE 0HVLDO_STARTUP_CURR_STATE 0 (LL_CLK_STATE)LL_CLK_STATE

Description

MT Status Register

Fields

BLESS_STATE

1’b0 - BLESS in DPSLP state 1’b1 - BLESS in ACTIVE state
MT_CURR_STATE

This register reflects the current state of the MT FSM 4’h0 - IDLE 4’h1 - BLERD_DEEPSLEEP 4’h2 - HVLDO_STARTUP 4’h3 - WAIT_CLK 4’h4 - BLERD_IDLE 4’h5 - SWITCH_EN 4’h6 - ACTIVE 4’h7 - ISOLATE 4’h8 - WAIT_IDLE 4’h9 - XTAL_DISABLE 4’hA - HVLDO_DISABLE
HVLDO_STARTUP_CURR_STATE

This register reflects the current state of the HVLDO Startup FSM 3’h0 - HVLDO_OFF 3’h1 - HVLDO_WAIT 3’h2 - HVLDO_SAMPLE 3’h3 - HVLDO_ENABLED 3’h4 - HVLDO_SET_BYPASS
LL_CLK_STATE

This bit indicates when the Link Layer registers are accessible upon a DSM exit. This bit should not be used after a DSM entry command has been issued. 1’b0 - Link Layer clock is not available 1’b1 - Link Layer clock is active

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data